SM4 acceleration processors, methods, systems, and instructions

摘要

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

主权项

1. A processor comprising:
a plurality of packed data registers; a decoder to decode an instruction, the instruction to indicate one or more source packed data operands, the one or more source packed data operands to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values; and an execution unit including at least some circuitry coupled with the decoder and coupled with the plurality of the packed data registers, the execution unit, in response to the instruction, to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination packed data register of the plurality of packed data registers that is to be indicated by the instruction.