| 摘要 |
PURPOSE:To obtain a phase locked oscillator where the phase difference between input and output is eliminated by controlling a voltage controlled oscillator by the sum of a signal proportional to the phase difference between an input clock signal and an output clock signal and a signal being the integration of the signal inversely proportional thereto. CONSTITUTION:An input clock signal inputted to a clock signal input terminal 10 is fed to a 1st and 2nd phase comparators 20, 30. On the other hand, the clock signal outputted to a clock signal output terminal 80 is fed to the 1st phase comparator 20 and the phase is inverted by a phase inverting circuit 40 and the result is fed to the 2nd phase comparator 30. The phase of the two kinds of clock signals inputted respectively are compared by the 1st and 2nd phase comparators 20, 30 and a voltage signal having a sawtoothed characteristic and the inverted sawtoothed characteristic proportional to the phase difference is outputted therefrom. Then a signal being the integration of an output of the 2nd phase comparator 30 by an integration device 50 is added to the output of the 1st phase comparator by an adder 60, the result is fed to a voltage controlled oscillator 70, and the oscillated frequency is controlled. |
