| 摘要 |
PURPOSE:To execute a fair and high speed bus adjustment by a simple adjustment circuit by interrupting an emergency request at the time of switching the bus cycle of a general request and making a bus using a request signal inactive by other bus master when a lock signal is made active. CONSTITUTION:The emergency bus using request signal (CBRH/) terminal of the bus masters 101-10N, a common general bus using request signal (CBRL/) terminal and bus clock signal (LOCK/) terminal are mutually connected and the bus using request signal (BREQ/) terminal is connected to a bus arbiter circuit 200 and the bus arbiter circuit 200 is connected to the bus using permission signal (BACK/) terminal of the bus masters 101-10N. the bus arbiter circuit 200 is constituted of a priority encoder and a decoder for applying a priority to a bus using request signal BREQ/ from the bus masters 101-10N and transmitting the using permission signal only to the request signal of the highest priority.
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