| 摘要 |
PURPOSE:To reduce gate input capacitance without lowering gm, and to improve the figure of a merit by partially forming a high concentration region having the same conductivity type as a gate region to a section just under the gate region shaped to the surface and on the side reverse to the gate region to a channel. CONSTITUTION:A low concentration region 2 having the same conductivity type as a P-type semiconductor base body 1 in high concentration is formed onto one main surface of the base body 1, a region 3 having a conductivity type reverse to the base body is formed, and a drain region 4 and a source region 5 having the conductivity type reverse to the base body are shaped into the reverse conductivity type region. A gate region 6 having the same conductivity type as the base body is formed, a high concentration region 7 having the same conductivity type as the base body is formed partially to a section just under the gate region and on the side reverse to the gate region 6 to a channel, and the gate region 6 and the high concentration region are connected electrically. Accordingly, a semiconductor device having large gm, small gate input capacitance and high performance is acquired only by adding a high-energy ion implantation process to the process of a junction type FET.
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