| 摘要 |
PURPOSE:To contrive the attainment of high speed for a DRAM by using a differential amplifier constituting a bipolar transistor (TR) as a driver TR as a bit line sense amplifier and using a row address signal inputted first to select a bit line and using a column address signal inputted next to select a read line. CONSTITUTION:When a row address strobe signal the inverse of RAS is trailed at an active cycle and a row address signal is fetched, a decoded signal phi1 is led and C<2>MOS inverters 231, 232 corresponding to a couple of bit line are in the operative state. The signal phi2 is led at the same time and a BICOMS differential amplifier 22 connected to the selected bit line pair is activated. Then the column address strobe signal, the inverse of CAS is trailed to decode a column address signal and a word line WL and a dummy word line DWL are led. Thus, the information transferred to bit line pair BL, the inverse of BL enters the amplifier 22 and is transferred to input/output lines I/O, the inverse of I/O. In constituting an I/O sense amplifier and a data output line by a BICOMOS, the information is extracted up to the data output terminal without any modification.
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