发明名称 SUPERVISORY CONTROL CIRCUIT FOR DIGITAL RECOVERY REPEATER
摘要 PURPOSE:To surely receive a control signal by giving an output of a timing component extraction circuit of a digital recovery repeater to an input of a peak detection circuit and connecting the output of the peak detection circuit to an input of a control signal reception circuit. CONSTITUTION:An output signal of an equalizing amplifier circuit 1 is given to a 1st input of the identification recovery circuit 2 and a input of a timing component extraction circuit 4 of a timing circuit 3. The output of the timing component extraction circuit 4 is connected to the input of a timing wave generating circuit 5 and a peak detection circuit 5. The output of the timing wave generating circuit 5 of the timing circuit 3 is connected to the 2nd input of the said identification recovery circuit 2. Moreover, the output of the peak detection circuit 6 is connected to the input of the control signal reception circuit. A signal D outputted to an output line 10 of the peak detection circuit 6 represents the signal detecting the peak of the signal C and the control signal A is accurately demodulated.
申请公布号 JPS63211944(A) 申请公布日期 1988.09.05
申请号 JP19870044173 申请日期 1987.02.27
申请人 NEC CORP 发明人 WATANABE SEIJI
分类号 H04L25/02;H04B3/36;H04L25/40 主分类号 H04L25/02
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