发明名称 Method and circuit arrangement for incrementing and decrementing events by means of an up/down counter
摘要 Known counters of this type are not capable of recording event signals which arrive simultaneously in time or overlapping one another. The invention provides a remedy in that the event signals of at least one of the directions of counting are stored and the forwarding of the stored event signals is disabled at the associated inputs during the presence of event signals for the other direction of counting. The invention is particularly applicable to indicating the level of loading of a shift register as buffer memory in the serial data transmission of data packets of different size.
申请公布号 DE3713940(A1) 申请公布日期 1988.11.03
申请号 DE19873713940 申请日期 1987.04.25
申请人 DEUTSCHE THOMSON-BRANDT GMBH 发明人 WESSOLLY,BERND,DIPL.-ING.;LUEDECKE,JOACHIM,DIPL.-ING.
分类号 H03K23/86;(IPC1-7):H03K21/02 主分类号 H03K23/86
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