| 摘要 |
<p>An apparatus for processing a digital signal includes a pair of data buses (11), a pair of digital processing circuits (12, 13) respectively connected to corresponding one of the data buses, and a control circuit (20) which simultaneously controls the digital processing circuits. To the digital processing circuits, an external storage including cyclic storage areas is connected. The digital processing circuits evaluate an actual address data for the cyclic storage areas of the external storage by means of predetermined arithmetic operation. The actual address data is outputted through the data buses and an external storage interface circuit (16) to the external storage. An address data being stored in a storage of the digital processing circuit is read. During one instruction cycle, the read address data is incremented or decremented, and when the result thereof is a boundary of the cyclic storage areas, a predetermined value is outputted from an ALU (28). A starting address is added to the predetermined value and a result thereof is outputted as the actual address data.</p> |
