| 摘要 |
A digital image processor 10 comprises a master controller 30 and a plurality of digital modules 34, 36, 38, 40 for storing and processing data. The master controller 30 controls the operation of the processing and storing modules 34, 36, 38, 40 via a control bus 32. A plurality of data buses A-I interconnects the processing and storing modules 34, 36, 38, 40. Within each module is a communication switch and a logic unit which is responsive to the control signal along the control bus 32 for connecting one or more of the data buses to the communication switch of the module. Dynamic reconfiguring of the system is thus possible. <IMAGE> |
