| 摘要 |
PURPOSE: To provide an SIMD array processor equipped with the multi- dimensional array of high-flexibility processing elements by providing a decode means programmable through a programmable correcting means and a fixed decode means. CONSTITUTION: The instruction of an array controller is parallelly received through a bus 18 to a processing element P(i, j). When any row and column are selected by lines 20i and 22j, a decoder 64 decodes the instruction and the designated instruction is executed by applying a control signal through control busrs 66, 68 and 70 to input and output side multiplexers (MPX) 62 and 56 and a control unit (ALU) 48. In this case, the decoder 64 is composed of a 1st section 72 in the form of a normal fixed decoder logic circuit and a 2nd programmable section in the form of a look-up table(LUT) 74. The selected bit of the macro instruction is locally corrected by the LUT 74, the locally corrected bit is formed, and the macro instruction bit and the locally corrected bit are decoded by the fixed decoder logic circuit 72. Thus, the parallel throughput of the SIMD array processor is improved.
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