| 发明名称 |
CHIP AND METHOD FOR TESTING A PROCESSING COMPONENT OF A CHIP |
| 摘要 |
In accordance with one embodiment, a chip is provided which includes an interface configured to receive test data and masking data, a processing component having a plurality of scan chains. Each scan chain is configured to generate a test response on the basis of a processing of the test data. The chip further includes a compression circuit configured to compress the test responses generated by the scan chains to form a compressed test response, and a signature generating circuit configured to generate a signature on the basis of the compressed test response, depending on whether the masking data specify that the compressed test response is to be masked. |
| 申请公布号 |
US2016377677(A1) |
申请公布日期 |
2016.12.29 |
| 申请号 |
US201615191553 |
申请日期 |
2016.06.24 |
| 申请人 |
Infineon Technologies AG |
发明人 |
TILLE Daniel;PFANNKUCHEN Ulrike;JANKE Marcus |
| 分类号 |
G01R31/3177;G01R31/317 |
主分类号 |
G01R31/3177 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A chip, comprising:
an interface configured to receive test data and masking data; a processing component having a plurality of scan chains, wherein each scan chain is configured to generate a test response on the basis of a processing of the test data; a compression circuit configured to compress the test responses generated by the scan chains to form a compressed test response; and a signature generating circuit configured to generate a signature on the basis of the compressed test response, depending on whether the masking data specify that the compressed test response is to be masked. |
| 地址 |
Neubiberg DE |
