| 摘要 |
<p>PURPOSE:To speed up access time and to reduce power by providing an address change detecting circuit, a variable load circuit to change the magnitude of a load according to a detected signal from the address change detecting circuit, and a bit line selecting circuit to select plural bit lines according to an address signal. CONSTITUTION:When an address is switched, the output voltage of an address change detecting circuit 14 becomes an L level, the load of a variable load circuit 15 becomes small, and a bit line current becomes large. Consequently, when a written cell S1 is switched to an unwritten cell S2, the rise of bit line voltage is speeded up. Thus, the access time can be speeded up. On the other hand, under a stationary state in which the address is never switched, the output voltage of the address change detecting circuit 14 becomes an H level constantly, the load of the variable load circuit 15 becomes large, and the bit line current becomes small. Thus, the power can be reduced.</p> |
