| 摘要 |
PURPOSE:To make chip size small and to shorten delay time due to wiring capacity by shortening wiring for clock pulse between a timing generator and unit cell. CONSTITUTION:Timing to store in the first storing section and timing to read out the content of memory from the second storing section are made equal to timing to precharge the second storing section of unit cell which is in the relation of unit cell and complementary address and timing to transfer the content of memory between storing sections, and unit cells in the relation of complementary address are arranged adjoining each other. For instance, row of unit cells is made in relation of complementary address, that is, if the 34th phase, unit cell 3 is placed adjacent to unit cell 1, and unit cell 4 is placed adjacent to unit cell 2. In this way, wiring between the timing generator 3 and unit cells 1- 3 can be shortened and simplified. |
