发明名称 |
COMMUNICATION EQUIPMENT |
摘要 |
PURPOSE:To simplify the synchronizing circuit and to reduce the synchronization acquisition time by providing a low speed clock generator and a high speed clock generator to switch the hopping speed. CONSTITUTION:A low speed clock generator 6 and a high speed clock generator 7 are provided and they are used switchingly. That is, an input to a reception antenna 1 is amplified by a high frequency amplifier 2 and fed to a mixer 4. Another input to the mixer 4 is an output of a local oscillator 3 and the output is hopped at a frequency parted by a difference of an intermediate frequency apart from an input of the reception antenna 1 with a digital output of a hopping pattern generator 5. Then the low speed clock generator 6 and a switch 15 are provided and the low speed clock generator 6 controls the hopping pattern generator 5 till the synchronization acquisition is established. Thus, the synchronizing circuit is simplified and the synchronization acquisition time is reduced. |
申请公布号 |
JPH02309833(A) |
申请公布日期 |
1990.12.25 |
申请号 |
JP19890130149 |
申请日期 |
1989.05.25 |
申请人 |
TECH RES & DEV INST OF JAPAN DEF AGENCY |
发明人 |
MUTO YOSHITAKA;SAWASA HIROYUKI;MURAKAMI MASAHIKO |
分类号 |
H04K1/04;H04B1/7156;H04J13/00 |
主分类号 |
H04K1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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