| 摘要 |
Multiple clock synthesizer comprising: (a) an oscillator means (10) for providing a train of pulses corresponding to a base signal; (b) a plurality of delay means (16A-16D) coupled to said oscillator means (10) each providing a different delay to said base signal to in turn provide a plurality of delayed clocking signals; (c) a plurality of register means (40) each having, a clocking input, a plurality of output taps, and load inputs and corresponding in number to said plurality of delay means each of said register means receiving on its clocking input a delayed clocking signal from an associated one of said plurality of delay means (16A-16D) and on its loading input; and (d) a binary number which is circulated in each of said plurality of register means as a function of the associated clocking signal to provide at said output a sequence of pulses each having a leading edge displacement defined by [1 divided by (the number of outputs in the clock delay section times the number of output per register)] times the element clock period. The number of outputs in the clock delay section corresponding to the number of registers used. |
