Non-volatile static RAM and method of operation thereof

摘要

A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.

主权项

1. A memory device, comprising:
a static random access memory (SRAM) circuit including a first data latch node and a second data latch node, the first data latch node configured to be maintained at a first voltage representing one bit of binary data and the second data latch node configured to be maintained at a second voltage representing one bit of complementary binary data; a non-volatile (NV) circuit including a first ferroelectric capacitor (F-Cap) coupled to the first data latch node and configured to store the one bit of binary data, wherein the first F-Cap is further coupled to a first bit-line and configured to output the one bit of binary data thereto; and a discharge circuit including first and second discharge transistors controllable by a common discharge signal, wherein a source terminal of the first discharge transistor is configured to be coupled to ground and a drain terminal of the first discharge transistor is coupled to the first F-Cap to provide a discharge path for charges accumulated thereat.