| 摘要 |
Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision.;A first normalization circuit (120) performs a first normalization, in which a plurality pieces of data, which have a common exponent and which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each of a plurality of cycles and the plurality of pieces of data inputted in each of the plurality of cycles are respectively normalized with the common exponent on the basis of a maximum exponent for the plurality of pieces of data inputted in a corresponding one of the plurality of cycle. A rounding circuit (130) outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed. A first storage circuit (140) stores a plurality of pieces of rounded data regarding the plurality of cycles in which the first normalization is performed and outputs a plurality of designated pieces of rounded data among the stored plurality of pieces of rounded data. A second normalization circuit (150) performs a second normalization, in which the plurality of designated pieces of rounded data are respectively normalized with an exponent which is common to the plurality of designated pieces of rounded data on the basis of the maximum exponents used in the first normalization for the plurality of designated pieces of rounded data and a maximum value of the maximum exponents, and outputs a result of the second normalization. |
| 主权项 |
1. An arithmetic processing apparatus comprising:
a first normalization circuit which performs a first normalization, in which a plurality pieces of data, which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each cycle and the plurality of pieces of data inputted in the cycle are respectively normalized on the basis of a maximum exponent for the plurality of pieces of data inputted in the cycle; a rounding circuit which outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed; a first storage circuit which stores a plurality of pieces of rounded data regarding a plurality of cycles in which the first normalization is performed and outputs a plurality of designated pieces of rounded data among the stored plurality of pieces of rounded data, the plurality of designated pieces of rounded data including pieces of rounded data outputted in different cycles; and a second normalization circuit which performs a second normalization, in which the plurality of designated pieces of rounded data are respectively normalized on the basis of the maximum exponents used in the first normalization for the plurality of designated pieces of rounded data and a maximum value of the maximum exponents, and outputs a result of the second normalization, wherein the second normalization circuit calculates, for each of the plurality of designated pieces of rounded data, a corrected exponent which is obtained by subtracting the maximum exponent used in the first normalization for a corresponding one of the plurality of designated pieces of rounded data from the maximum value of the maximum exponents used in the first normalization for the plurality of designated pieces of rounded data, and normalizes the plurality of designated pieces of rounded data based on the corrected exponents respectively, wherein n (n is an integer which is equal to or greater than 2) pieces of the fixed-point number representation data or the mantissa portion data of block floating-point number representation are inputted in each cycle, in a first normalization phase, the first normalization circuit normalizes n pieces of data on the basis of the maximum exponent for the n pieces of data, in each cycle, the rounding circuit outputs n pieces of rounded data which are obtained by reducing a bit width of respective one of the n pieces of data on which the first normalization is performed, in each cycle, the first storage circuit stores (m×n) pieces of rounded data for m (m is an integer which is equal to or greater than 2) cycles in the first normalization phase, and outputs n designated pieces of rounded data which are selected from the stored rounded data, in each cycle, in a second normalization phase after the first normalization phase, the second normalization circuit selects n maximum exponents for cycles respectively corresponding to the n designated pieces of rounded data out of m maximum exponents for the m cycles, calculates n corrected exponents by subtracting respective one of the n maximum exponents from the maximum value of the n maximum exponents, and normalizes the n pieces of designated rounded data based on the n corrected exponents respectively, in each cycle, in the second normalization phase, a cycle in which k-th (k is an integer which is equal to or greater than 1 and equal to or smaller than n) piece of rounded data in the normalization by the second normalization circuit is generated and a cycle corresponding to the maximum exponent used to calculate the corrected exponent in the normalization of the k-th rounded data by the second normalization circuit are the same. |
