发明名称 TESTING SYSTEM FOR LOGIC CIRCUIT HAVING LOOP SCAN PATH
摘要 PURPOSE:To enable a high speed diagnosis with hardwares by providing one counter and issuing a scan clock and operation clock by a control circuit in accordance with a setting mode. CONSTITUTION:In an usual operating time, a test mode and scan mode are both set to OFF ('0') by a service processor 2. So, an AND gate 144 is normally opened by the output of an inverter 141 and an AND gate 146 is normally closed, then the operation clocks are always issued in latch circuits 10a-10c independent of the contents of a subtracting counter 15 and the scan clock is not issued. The scan made is issued from the processor 2 as well as the test mode defining the operation, and the issue of scan pulses and operation clocks in the quantities set on the counter 15 is made possible by means of supplying the output of counter 15 to the gates 144, 146 with changing-over according to the scan mode. Consequently, only one set of counter 15 is enough for this procedure, and the quantity of hardwares can be reduced and also the high speed diagnosis can be performed.
申请公布号 JPH03239974(A) 申请公布日期 1991.10.25
申请号 JP19900037950 申请日期 1990.02.19
申请人 FUJITSU LTD 发明人 YAMAGUCHI SHOJI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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