发明名称 PHASE LOCKED LOOP OSCILLATING CIRCUIT
摘要 PURPOSE:To keep the accuracy of a frequency of an output clock signal even after interruption of an input clock signal by providing a constant voltage supply circuit to a voltage controlled oscillator and giving a control voltage to the voltage supply circuit when the interruption of the input clock signal is detected. CONSTITUTION:So long as a predetermined clock signal is inputted to a terminal 1 of a switch 14, the switch 14 is closed by a control signal of a clock interruption detection circuit 17 and a switch 18 is opened. An output of a low pass filter 13 is inputted as it is to a voltage control input terminal of a voltage controlled oscillator 15 and a clock signal having an oscillating frequency corresponding to the input control voltage is outputted from a terminal 2. When a detection circuit 17 detects interruption of the input clock signal, the switch 18 is closed at first to connect itself to the constant voltage supply circuit 20. Then the input voltage of the oscillator 15 is filed to a prescribed value by allowing the detection circuit 17 to open the switch 14 and the output of the oscillator 16 outputs the clock signal consecutively at a prescribed frequency without causing rapid disturbance.
申请公布号 JPH047911(A) 申请公布日期 1992.01.13
申请号 JP19900110903 申请日期 1990.04.25
申请人 NEC CORP 发明人 TANAKA HIROTADA
分类号 H03L7/14 主分类号 H03L7/14
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