发明名称 Single field effect transistor capacitor-less memory device and method of operating the same
摘要 A single field effect transistor capacitor-less memory device, and method of operating the same, including a drain region, a source region, an intrinsic channel region between the drain region and the source region forming the single field effect transistor and a base. The device further includes a fin structure comprising the source region, the intrinsic channel and the drain region, the fin structure extending outwardly from the base, and a double gate comprising a first gate connected to a first exposed lateral face of the intrinsic channel region for transistor control, and a second gate connected to a second exposed lateral face of the intrinsic channel region to generate a potential well for storing mobile charge carriers permitting memory operation, the first gate and the second gate being asymmetric for asymmetric electrostatic control of the device.
申请公布号 US9508854(B2) 申请公布日期 2016.11.29
申请号 US201414507487 申请日期 2014.10.06
申请人 ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) 发明人 Biswas Arnab;Dagtekin Nilay;Ionescu Mihai Adrian
分类号 G11C7/22;H01L29/78;H01L27/12;H01L27/108;G11C11/404 主分类号 G11C7/22
代理机构 Sheridan Ross P.C. 代理人 Sheridan Ross P.C.
主权项 1. A single field effect transistor capacitor-less memory device including: a drain region; a source region; an intrinsic channel region between the drain region and the source region forming the single field effect transistor; a base; wherein the device further includes: a fin structure (FIN) comprising the source region, the intrinsic channel and the drain region, the fin structure extending outwardly from the base; and a double gate comprising a first gate (G1) connected to a first exposed lateral face of the intrinsic channel region for transistor control, and a second gate (G2) connected to a second exposed lateral face of the intrinsic channel region to generate a potential well for storing mobile charge carriers permitting memory operation, the first gate (G1) and the second gate (G2) being independent and asymmetric gates with respect to each other for asymmetric electrostatic control of the device.
地址 Lausanne CH