Wiring board and method for manufacturing same

摘要

To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43, a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.

主权项

1. A wiring board, comprising
a laminated body where respective one or more layers of insulating layers and conductor layers are laminated, the conductor layer in an outermost layer of the laminated body including a plurality of connecting terminal portions disposed in a mounting area for a semiconductor chip so as to flip-chip mount the semiconductor chip, a solder resist layer being disposed as the insulating layer in an outermost layer of the laminated body, the plurality of connecting terminal portions including a surface exposed through an opening portion formed in the solder resist layer, wherein for each of the plurality of the connection terminal portions exposed through the opening portion, the connecting terminal portion includes a connection region and a wiring region, the connection region being to connect to a connecting terminal of the semiconductor chip via solder, the wiring region exposed through the opening portion and being disposed to extend from the connection region along a planar direction, and the solder resist layer includes a side-surface covering portion and a projecting wall portion within the opening portion, the side-surface covering portion covering a side surface of each connecting terminal portion, the projecting wall portion being integrally formed with the side-surface covering portion, the projecting wall portion being disposed to project so as to intersect with the connection region of each connecting terminal portion and divide each connecting terminal portion into the connection region and the wiring region with the connection regions arrayed alternately on either side of the projecting wall portion to connect the semiconductor chip.