| 摘要 |
<p>PURPOSE:To realize low speed synchronization serial/parallel conversion with simple constitution without use of an elastic storage ES by writing and reading a parallel data being an output of a shift register to/from a latch in the S/P timing and inputting the result to an FF and outputting the parallel data synchronously with a low speed clock. CONSTITUTION:A DFFB1 of an edge detection circuit 2 receives a low speed clock (c) and a high speed clock (b) of a serial data (a) inputted to a shift register A and outputs an output (e). A DFFB2 outputs an output (f), an output (g) of an AND gate C is fed to a shift register D of an S/P timing generating circuit 3 at the leading of the clock (b) and a signal (h) is obtained from the shift register D. A DFFB3 of a latch 4 receives the signal (h) to write parallel data d1-d4 being outputs of the register A and parallel data i1-i4 are read from the latch 4. A DFFB4 of an output circuit 5 receives the parallel data i1-i4 and outputs data j1-j4 synchronously with the low speed clock (c).</p> |
