| 摘要 |
<p>PURPOSE:To satisfy a decided delay characteristic by generating a control the delay time control voltage proportional to a pulse frequency so as to control the delay time of a variable delay element. CONSTITUTION:A delay circuit 2 consists of a flip-flop F1 to synchronize an input signal 1 with a clock pulse C, a delay section 21 delaying a synchronized signal and an F/V conversion circuit 31 generating a voltage proportional to the clock pulse frequency. Moreover, the delay section 21 consists of two buffers B21, B22 having a fixed delay time and a variable delay element DL 21 inserted between both the buffers. The frequency of the clock pulse D and the delay time of the variable delay element 21 are set so that the delay time is almost inversely proportional with respect to the frequency. Thus, the standards of the delay characteristic decided to the integrated circuit device are satisfied.</p> |
