Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same

摘要

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

主权项

1. A semiconductor chip, comprising:
a plurality of cells positioned in a side-by-side manner, the plurality of cells including linear-shaped conductive structures formed in a first chip level and linear-shaped conductive structures formed in a second chip level, the linear-shaped conductive structures formed in the first chip level oriented to extend lengthwise in a first direction, the linear-shaped conductive structures formed in the second chip level oriented to extend lengthwise in the first direction, wherein the linear-shaped conductive structures in the first chip level are positioned in accordance with a first uniform pitch across the plurality of cells such that a distance as measured in a second direction perpendicular to the first direction between lengthwise centerlines of any two of the linear-shaped conductive structures in the first chip level is an integer multiple of the first uniform pitch, wherein the linear-shaped conductive structures in the second chip level are positioned in accordance with a second uniform pitch across the plurality of cells such that a distance as measured in a second direction perpendicular to the first direction between lengthwise centerlines of any two of the linear-shaped conductive structures in the second chip level is an integer multiple of the second uniform pitch, wherein each of the plurality of cells is configured in accordance with any one of an even integer number of possible phases, wherein each of the even integer number of possible phases for a given one of the plurality of cells is defined by a specific spatial relationship between the first uniform pitch locations in the first chip level and the second uniform pitch locations in the second chip level across the given one of the plurality of cells.