| 摘要 |
A processor apparatus comprising: cryptographic and video accelerators; a memory controller; and a processor 100, comprising: first 110 and second 120 plurality of cores; wherein the second plurality of cores is heterogeneous to and have lower power consumption than the first; an interconnect to couple the first cores, the second cores, and a shared cache memory coupled to at least the first cores; and a logic to cause a core of the second plurality of cores to execute an operation, wherein based at least in part on performance level of the core of the second cores, the logic is to cause an execution state of the core of the second cores to be transferred to a core of the first plurality of cores to enable the core of the first cores to execute the operation. Also disclosed is a method and a computer readable storage medium with instructions for a system which, when executed, causes the processor to execute the operation defined previously. |
