发明名称 VISUAL FRAME BUFFER ARCHITECTURE
摘要 An apparatus for processing visual data is comprised of a first storage means for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first storage means by a data bus and through a storage bus. Means for receiving a second storage means for storing a second bit plane of visual data in a second format different from the first format is also provided. The receiving means is adapted to couple a second storage means to the graphics controller by a data bus and through a storage bus. Means for forming a merged pixel stream from visual data stored on the first and second storage means are also included. Means, coupled to the graphics controller, are provided for displaying the merged pixel stream. In a further embodiment, an apparatus for processing visual data is comprised of a first storage means for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first storage means by a data bus and through a storage bus. A second storage means coupled to the graphics controller by a data bus and through a storage bus is provided for storing a second bit plane of visual data in a second format different from the first format. Means for forming a merged pixel stream from visual data stored on the first and second storage means are also included. Means, coupled to the graphics controller, are provided for displaying the merged pixel stream.
申请公布号 WO9321623(A1) 申请公布日期 1993.10.28
申请号 WO1993US02773 申请日期 1993.03.24
申请人 INTEL CORPORATION 发明人 LIPPINCOTT, LOUIS, A.
分类号 H04N5/262;G09G5/02;G09G5/06;G09G5/36;G09G5/39;G09G5/397;G09G5/399;H04N5/445;H04N9/75;(IPC1-7):G09G1/16;H04N5/275 主分类号 H04N5/262
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