发明名称 System, method, and computer program product for input/output buffer modeling
摘要 The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.
申请公布号 US9460250(B1) 申请公布日期 2016.10.04
申请号 US201213562092 申请日期 2012.07.30
申请人 Cadence Design Systems, Inc. 发明人 Schutt-Aine Jose Emmanuel;Nagle Dennis;Al-Hawari Feras;Varma Ambrish Kant;Tan Jilin;Liu Ping;Wu Shangli;Meng Yubao;Zhao Qi;Zhou Zhongyong
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Holland & Knight LLP 代理人 Holland & Knight LLP ;Whittenberger, Esq. Mark H.
主权项 1. A computer-implemented method for transient simulation of an input/output buffer model comprising: generating, using one or more computing devices, an input/output buffer data file associated with a first Input/Output Buffer Information model of a first electrical circuit; determining, using one or more computing devices, a node voltage and a branch current associated with the first electrical circuit using, at least in part, a latency insertion method, wherein determining a node voltage and a branch current associated with the first electrical circuit includes alternately computing the node voltage and the branch current as time progresses in a leapfrog manner using a leapfrog time stepping formulation; and performing, using the one or more computing devices, one or more simulations on a second Input/Output Buffer Information model of a second electrical circuit, the one or more simulations on the second electrical circuit incorporating, at least in part, at least one coefficient determined from the input/output buffer data file of the first electrical circuit and the latency insertion method, wherein the first electrical circuit and the second electrical circuit are different.
地址 San Jose CA US