发明名称 |
HARDWARE AND SOFTWARE SOLUTIONS TO DIVERGENT BRANCHES IN A PARALLEL PIPELINE |
摘要 |
A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler arranges instructions within the identified loop into very large instruction words (VLIW's). At least one VLIW includes instructions intermingled from different basic blocks between the given divergence point and a corresponding convergence point. The compiler generates code wherein when executed assigns at runtime instructions within a given VLIW to multiple parallel execution lanes within a target processor. The target processor includes a single instruction multiple data (SIMD) micro-architecture. The assignment for a given lane is based on branch direction found at runtime for the given lane at the given divergent point. The target processor includes a vector register for storing indications indicating which given instruction within a fetched VLIW for an associated lane to execute. |
申请公布号 |
EP2951682(A4) |
申请公布日期 |
2016.12.28 |
申请号 |
EP20140746711 |
申请日期 |
2014.01.28 |
申请人 |
Advanced Micro Devices, Inc. |
发明人 |
YAZDANI, Reza |
分类号 |
G06F9/38;G06F9/30;G06F9/45 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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