Debug circuit for an integrated circuit

摘要

An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

主权项

1. An integrated circuit operable in functional and debug modes and having an input/output (IO) pad, comprising:
a pad control register for storing pull-type select control and pull-enable control bits and generating pull-type select control and pull-enable control signals when the integrated circuit is in the functional mode; a first logic gate having a first input terminal for receiving a debug control signal, a second input terminal for receiving a reference signal, and an output terminal for generating a first signal when the integrated circuit is in the debug mode; a second logic gate having a first input terminal connected to the output terminal of the first logic gate for receiving the first signal, a second input terminal connected to the pad control register for receiving the pull-type select control signal, and an output terminal for generating the first signal as a pull-type select signal when the integrated circuit is in the debug mode; a third logic gate having a first input terminal for receiving a functional signal of the integrated circuit, a second input terminal for receiving the reference signal, and an output terminal for generating a functional control signal when the integrated circuit is in the debug mode; a fourth logic gate having a first input terminal for receiving the debug control signal, a second input terminal connected to the output terminal of the third logic gate for receiving the functional control signal, and an output terminal for generating a second signal when the integrated circuit is in the debug mode; a fifth logic gate having a first input terminal connected to the output terminal of the fourth logic gate for receiving the second signal, a second input terminal connected to the pad control register for receiving the pull-enable control signal, and an output terminal for generating the second signal as a pull-enable signal when the integrated circuit is in the debug mode; and a pad configuration register, connected to the output terminals of the second and fifth logic gates for receiving the corresponding pull-type select and pull-enable signals, and to the IO pad for configuring the IO pad in at least one of logic high, logic low, and high impedance states when the integrated circuit is in the debug mode, wherein at least one of the logic high, logic low, and high impedance states of the IO pad indicates a state of the functional signal of the integrated circuit.