发明名称 |
MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK |
摘要 |
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network. |
申请公布号 |
EP3109769(A2) |
申请公布日期 |
2016.12.28 |
申请号 |
EP20160174345 |
申请日期 |
2013.11.21 |
申请人 |
Coherent Logix, Incorporated |
发明人 |
DOBBS, Carl S.;TROCINO, Michael R. |
分类号 |
G06F15/173;G06F15/78 |
主分类号 |
G06F15/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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