发明名称 |
INPUT/OUTPUT BUFFER CIRCUIT |
摘要 |
An input/output (I/O) buffer circuit includes an I/O unit, a first register and a second register. The I/O unit selectively transmits digital signals and analog signals according to a enable signal, and selectively receives signals and outputs signals at an I/O terminal according to a second enable signal. The first register latches a first control signal received before power is turned off, and outputs the first enable signal corresponding to the first control signal to the I/O unit when power is turned on. The second register latches a second control signal received before power is turned off, and outputs the second enable signal corresponding to the second control signal to the I/O unit when power is turned on. |
申请公布号 |
US2016269030(A1) |
申请公布日期 |
2016.09.15 |
申请号 |
US201615011653 |
申请日期 |
2016.01.31 |
申请人 |
Nuvoton Technology Corporation |
发明人 |
WANG Cheng-Chih |
分类号 |
H03K19/173;H03K19/0185 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
1. An input/output (I/O) buffer circuit comprising:
an I/O unit configured to selectively transmit digital signals and analog signals according to a first enable signal, and selectively receive signals and output signals at an I/O terminal according to a second enable signal; a first register configured to latch a first control signal received before power is turned off, and output the first enable signal corresponding to the first control signal to the I/O unit when power is turned on; and a second register configured to latch a second control signal received before power is turned off, and output the second enable signal corresponding to the second control signal to the I/O unit when power is turned on. |
地址 |
Hsinchu TW |