| 摘要 |
PROBLEM TO BE SOLVED: To allow shift registers provided to both two substrates to be driven while being synchronized without adjusting generation timing of clock signals.SOLUTION: A first clock control section 130 generates a first output clock signal corresponding to logical operation (for example, a logical product) of a first clock signal CLK1 (CLK11) supplied via a first terminal 101 and a second clock signal CLK2 (CLK21) supplied via a second terminal 201, a fourth conduction section 220 and a second conduction section 120, and supplies the first output clock signal to a first shift register 140. A second clock control section 230 generates a second output clock signal corresponding to logical operation (for example, a logical product) of a first clock signal CLK1 (CLK12) supplied via the first terminal 101, a first conduction section 110 and a third conduction section 210 and a second clock signal CLK2 (CLK22) supplied via the second terminal 201 and supplies the second output clock signal to a second shift register 240.SELECTED DRAWING: Figure 2 |
