发明名称 METHOD AND APPARATUS FOR UTILIZING ESTIMATIONS FOR REGISTER RETIMING IN A DESIGN COMPILATION FLOW
摘要 A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.
申请公布号 EP3109780(A1) 申请公布日期 2016.12.28
申请号 EP20160172777 申请日期 2016.06.03
申请人 Altera Corporation 发明人 Sinnadurai, Nishanth;Gamsa, Benjamin
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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