| 发明名称 |
MULTIPLE CORE COMPUTER PROCESSOR WITH GLOBALLY-ACCESSIBLE LOCAL MEMORIES |
| 摘要 |
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores. |
| 申请公布号 |
US2016371226(A1) |
申请公布日期 |
2016.12.22 |
| 申请号 |
US201615243634 |
申请日期 |
2016.08.22 |
| 申请人 |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA |
发明人 |
Shalf John;Donofrio David;Oliker Leonid |
| 分类号 |
G06F15/78;G06F12/1081;G06F12/0842;G06F12/0811;G06F12/0815 |
主分类号 |
G06F15/78 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A multi-core computer processor comprising:
a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture; a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores; and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores. |
| 地址 |
Oakland CA US |
