发明名称 |
Vertical memory devices and methods of manufacturing the same |
摘要 |
Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions. |
申请公布号 |
US9431414(B2) |
申请公布日期 |
2016.08.30 |
申请号 |
US201414517025 |
申请日期 |
2014.10.17 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Jang Byong-Hyun;Yoo Dong-Chul;Hwang Ki-Hyun;Nam Phil-Ouk;Ahn Jae-Young |
分类号 |
H01L27/115;H01L29/66;H01L29/792 |
主分类号 |
H01L27/115 |
代理机构 |
Myers Bigel & Sibley, P.A. |
代理人 |
Myers Bigel & Sibley, P.A. |
主权项 |
1. A nonvolatile memory device, comprising:
at least four cylindrical-shaped channel regions extending vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate; a charge storage layer on an outer sidewall of each of said at least four cylindrical-shaped channel regions; a plurality of vertically-stacked gate electrodes extending adjacent each of said at least four cylindrical-shaped channel regions; and a plurality of bit lines extending over said at least four cylindrical-shaped channel regions, said plurality of bit lines including at least first, second and third bit lines electrically coupled to respective ones of said at least four cylindrical-shaped channel regions; and wherein the first, second and third bit lines extend parallel to each other and in a direction oblique relative to all sides of the at least one rhomboid when viewed in the vertical direction. |
地址 |
KR |