PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR PRODUCING THE SAME

摘要

A pillar-shaped semiconductor memory device includes an i-layer substrate and silicon pillars formed on the i-layer substrate. Tunnel insulating layers, a data charge storage insulating layer, an interlayer insulating layer, and gas layers are formed so as to surround outer peripheries of the silicon pillars. Word lines that are separated from each other by interlayer insulating layers are formed so as to surround outer peripheries of the gas layers in a direction perpendicular to an upper surface of the i-layer substrate.

主权项

1. A pillar-shaped semiconductor memory device comprising:
a semiconductor substrate; a first semiconductor pillar disposed on the semiconductor substrate and extending in a direction perpendicular to a surface of the semiconductor substrate; a tunnel insulating layer surrounding an outer periphery of the first semiconductor pillar; a data charge storage insulating layer surrounding an outer periphery of the tunnel insulating layer; a first interlayer insulating layer surrounding an outer periphery of the data charge storage insulating layer; a space surrounding an outer periphery of the first interlayer insulating layer; at least one stacked material layer that surrounds an outer periphery of the space and that is formed in a direction perpendicular to the surface of the semiconductor substrate, the stacked material layer including a first conductor layer and a second interlayer insulating layer; and a second conductor layer that is formed on the outer periphery of the first semiconductor pillar and on the at least one stacked material layer, that supports a side face of the first interlayer insulating layer, and that seals the space, wherein the first interlayer insulating layer and the space insulate the first conductor layer from the data charge storage insulating layer, the first interlayer insulating layer insulates the second conductor layer from the data charge storage insulating layer, and data writing and erasing due to data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer or data charge retention by the data charge storage insulating layer is performed by application of a voltage to the first conductor layer.