| 发明名称 |
Stacked die integrated circuit |
| 摘要 |
An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another. |
| 申请公布号 |
US9418924(B2) |
申请公布日期 |
2016.08.16 |
| 申请号 |
US201414220912 |
申请日期 |
2014.03.20 |
| 申请人 |
Invensas Corporation |
发明人 |
Woychik Charles G.;Uzoh Cyprian Emeka;Zhang Ron;Buckminster Daniel;Gao Guilian |
| 分类号 |
H01L21/30;H01L23/498;H01L21/52;H01L21/78;H01L23/48;H01L23/00;H01L25/065;H01L21/768;H01L21/304;H01L23/13 |
主分类号 |
H01L21/30 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a package substrate having a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate; a plurality of bond via array wires coupled to the first plurality of via structures at the lower surface of the package substrate; a die having a second plurality of via structures extending to a lower surface of the die; wherein the lower surface of the die faces the upper surface of the package substrate in an integrated circuit package; wherein the package substrate does not include a redistribution layer; and wherein the die and the package substrate are coupled to one another. |
| 地址 |
San Jose CA US |
