发明名称 メモリ装置、演算処理装置、及びキャッシュメモリの制御方法
摘要 PROBLEM TO BE SOLVED: To variably set a data size of continuous access from a cache to a main memory.SOLUTION: A memory device includes: a write control circuit which when storing a single line in a data array in accordance with a cache fill request in the single line, sets corresponding management data of a management data array to a first state, and when storing a plurality of continuous lines in the data array in accordance with a cache fill request in the plurality of continuous lines, sets the corresponding management data of the management data array to a second state; and an access control circuit which when the corresponding management data of the management data array indicates the first state in write back, generates a request for writing cache data to be ejected as a single line, and when the corresponding management data of the management data array indicates the second state, generates a request for writing cache data of the data array to be integrated with the cache data to be ejected and the cache data to be ejected as a plurality of continuous lines.
申请公布号 JP5978814(B2) 申请公布日期 2016.08.24
申请号 JP20120153972 申请日期 2012.07.09
申请人 富士通株式会社 发明人 渡辺 慎吾
分类号 G06F12/0802;G06F12/08 主分类号 G06F12/0802
代理机构 代理人
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