发明名称 電界効果トランジスタの製造方法
摘要 PROBLEM TO BE SOLVED: To shorten gate length of an FET using a nanowire.SOLUTION: On an insulation layer 121a, a negative type resist layer 124 is formed in a state covering a lower gate electrode 122 and a coated nanowire 103. A positive type resist layer 125 is formed on the negative resist layer 124. Source and drain formation regions 201 at both ends of the coated nanowire 103 are irradiated with electron beams, so that the positive type resist layer 125 and the negative type resist layer 124 are simultaneously exposed.
申请公布号 JP6046590(B2) 申请公布日期 2016.12.21
申请号 JP20130226603 申请日期 2013.10.31
申请人 日本電信電話株式会社 发明人 佐々木 智;舘野 功太;章 国強;原田 裕一
分类号 H01L29/786;H01L21/027;H01L21/20;H01L21/28;H01L21/336;H01L21/768;H01L29/41;H01L29/417;H01L29/423;H01L29/49 主分类号 H01L29/786
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