发明名称 半導体装置
摘要 Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.
申请公布号 JP6047297(B2) 申请公布日期 2016.12.21
申请号 JP20120088373 申请日期 2012.04.09
申请人 ルネサスエレクトロニクス株式会社 发明人 加藤 浩朗;工藤 弘儀;守屋 太郎;打矢 聡
分类号 H01L29/78 主分类号 H01L29/78
代理机构 代理人
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