发明名称 ストレージシステム及び記憶制御方法
摘要 A storage system includes an expander sequence including a plurality of expanders coupled in series, a plurality of storage devices coupled to the expander sequence, first and second initiator devices coupled to the expander sequence, and a processor. The processor selects an optimal path, with respect to a transmission destination device of a command among the plurality of storage devices and the plurality of expanders, between the optimal path which is an initiator device with fewer expanders in a distance to the transmission destination device and a roundabout path which is an initiator device with more expanders in a distance to the transmission destination device, and transmits the command to the transmission destination device through the selected optimal path.
申请公布号 JP6049891(B2) 申请公布日期 2016.12.21
申请号 JP20150535216 申请日期 2013.09.05
申请人 株式会社日立製作所 发明人 鷲谷 幸司;新田 敏裕
分类号 G06F13/14;G06F3/06;G06F13/10;G06F13/36 主分类号 G06F13/14
代理机构 代理人
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