发明名称 バイアス回路
摘要 A bias circuit includes: a reference current generation circuit that has a first reference-current element disposed in a first current path and has a second reference-current element disposed in a second current path; a first current mirror circuit that has a first transistor connected in series with the first reference-current element and has a second transistor connected in series with the second reference-current element; a third reference-current element disposed in a third current path disposed between the power supply terminal and the reference-current element; a third transistor connected in series with the third reference-current element; a bypass capacitor connected between the power supply terminal and a second node connected to a control terminal of the third transistor; an activation circuit connected to the first node; and a first switch connected between the first node and the second node.
申请公布号 JP6048289(B2) 申请公布日期 2016.12.21
申请号 JP20130083262 申请日期 2013.04.11
申请人 富士通株式会社 发明人 中本 裕之
分类号 G05F3/26;H03F3/345 主分类号 G05F3/26
代理机构 代理人
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