发明名称 Cache coherency
摘要 An information processing system has several cache memories. A directory stores which caches store which addresses in memory. Multiple memory addresses map to a group of entries in the directory. When a new line is read into a cache, a new entry is added to the directory. If the address of the line maps to a group of directory entries, which is full, one of the entries in the group is evicted. The entry to evict is chosen based on the cache indicated in the directory entry. Messages may be sent to a cache to verify that the cache is storing a particular line indicated in the directory. In this case, the directory entry to evict may be chosen based on the number of times each cache has responded that it does not store a line that the directory indicates it does. The directory entry may also be chosen based on the turnover of lines in each cache.
申请公布号 GB2539383(A) 申请公布日期 2016.12.21
申请号 GB20150009424 申请日期 2015.06.01
申请人 ARM Limited 发明人 Andrew David Tune;Sean James Salisbury
分类号 G06F12/0817;G06F12/08 主分类号 G06F12/0817
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