MULTIPLE PROCESSOR CORE INTERRUPT PRIORITY LEVELS

摘要

A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.

主权项

1. A processor system comprising
at least two processor cores; an interrupt controller comprising interrupt priority registers configured for registering interrupt priority levels of the respective processor cores; and at least two task timers, each task timer being associated with a respective processor core; each task timer comprising
a counter configured for producing a counter value,a timeout value register configured for storing a timeout value, anda tidemark value register configured for storing a tidemark value smaller than the timeout value, wherein the tidemark value indicates elapsed time; each task timer being configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value, wherein the tidemark signal indicates elapsed time; wherein the interrupt controller is configured for increasing the interrupt priority level of a processor core in response to a tidemark signal of the associated task timer; and wherein the interrupt controller is configured for decreasing the interrupt priority level of a processor core in response to a timeout signal of the associated task timer.