| 摘要 |
PROBLEM TO BE SOLVED: To receive serial data stably.SOLUTION: A multiplication circuit 30 multiplies a bit clock BCK by N (N is a natural number) to generate a system clock PLLCK. A first counter 12 counts the system clock PLLCK and resets a count value CNT1 thereof to an initial value each time the count value reaches a set value D. A counter clear circuit 16 asserts a counter clear signal CNT_CLR each time the count value CNT1 of the first counter 12 reaches a prescribed value. A second counter 56 counts the system clock PLLCK and resets a count value to an initial value each time the counter clear signal CNT_CLR is asserted. An Lch latch 52 latches parallel data from a shift register 14 synchronously with the counter clear signal CNT_CLR. A cycle setting unit 70 dynamically sets the set value Dof the first counter CNT1. |
