LOW POWER, LOW READ DISTURBANCE NONVOLATILE MEMORY DEVICE

摘要

A non-volatile memory device is provided to reduce the size of layout by using the isolation transistor instead of the isolating region between the active areas. A memory cell array(110) comprises the first and second page regions(110a,110b). The first and second page regions are connected to the same word line. A latch circuit(140) provides first page data in the program operation in response to the first address to the first page region. The latch circuit provides the second page data in response to the second address to the second page region. A bit line switching circuit(130) comprises the first and second bit line switching circuits(130a,130b). A plurality of bit lines electrically connected to the first page region are selected by the first bit line switching circuit. A plurality of bit lines electrically connected to the second page region are selected by he second bit line switching circuit.