发明名称 エンコーダ、デコーダ及び方法
摘要 There is provided an encoder and decoder for encoding and decoding input data (D1, D2 or D3) to generate corresponding encoded output data (D2 or D3, D5). The encoder includes a data processing arrangement, optionally for analyzing a range of values present in the input data (D1) to determine at least one pre- and/or post-pedestal value, optionally to translate the input data (D1) using the at least one pre- and/or post-pedestal value to generate translated data, and then to apply a form of ODelta coding to the data, optionally translated data, to generate processed data, and to combine the processed data and optionally the at least one pre- and/or post-pedestal value for generating the encoded output data (D2 or D3). The decoder includes a data processing arrangement for processing the encoded data (D2 or D3), optionally to extract therefrom at least one pre- and/or post-pedestal value.
申请公布号 JP6045123(B2) 申请公布日期 2016.12.14
申请号 JP20150559442 申请日期 2014.02.27
申请人 グルロジック マイクロシステムズ オーワイGurulogic Microsystems Oy 发明人 カレヴォ オッシ
分类号 H03M7/36;H03M7/40 主分类号 H03M7/36
代理机构 代理人
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