| 摘要 |
A test pattern is provided to precisely measure the depth of a recess of a transistor by using a test pattern in a transistor having a recess gate of a three-dimensional structure wherein the test pattern is to measure the recess depth of the transistor. A P-type silicon substrate(200) functions as a first electrode wherein a plurality of grooves are formed in the P-type silicon substrate. A dielectric layer(220) is formed on the P-type silicon substrate including the surface of the groove. A polysilicon layer(240) is formed on the P-type silicon substrate including the dielectric layer to fill the grooves, functioning as a second electrode. The depth of the groove is measured from the capacitance among the P-type silicon substrate, the dielectric layer and the polysilicon layer. The P-type silicon substrate can have a size of 1x1-20x20 micrometer^2.
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