| 摘要 |
A method for fabricating a semiconductor device is provided to avoid a self-align contact defect in a peripheral circuit region by simultaneously forming a bit-line contact hole exposing a landing plug in a cell region and a bit-line contact hole exposing a semiconductor substrate in a peripheral circuit region. A gate(108) is formed on a semiconductor substrate(100) in which a cell region and a peripheral circuit region are defined. A landing plug(118) is formed between the gates in the cell region, and an interlayer dielectric is formed on the resultant structure. The interlayer dielectric is etched by a photolithography process using a first bit-line contact mask so that a first bit-line contact hole exposing the landing plug in the cell region is formed while a second bit-line contact hole exposing the semiconductor substrate in the peripheral circuit region is formed. The interlayer dielectric is etched by a photolithography process using a second bit-line contact mask to form a third bit-line contact hole exposing the gate in the peripheral circuit region. The gate is a stack structure of a gate polysilicon layer(102), a gate electrode layer(104) and a gate hard mask layer(106).
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