| 摘要 |
An apparatus comprises argument reduction circuitry to perform an argument reduction operation; and reduce and round circuitry to generate, from a supplied floating point value, a modified floating point value for input to the argument reduction circuitry. The reduce and round circuitry modifies a significand with a specified rounding applied to produce a truncated significand for the modified floating point value, where the truncated significand N bits shorter than the supplied floating point significand. The specified value N is such that the argument reduction operation performed using the modified floating point value inhibits the round-off error in a result of the argument reduction operation, and N may be such that the modified floating point value has an error bound of less than 1 unit of least precision (ULP) of the N-bits shorter truncated significand. The reduce and round circuitry may inject a rounding value at an Nth bit of the significand to produce a rounded value, then to form the truncated significand as the most significand M-N bits of the round value. The argument reduction operation may be a multiply-accumulate operation. |
